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|Title:||Asynchronous phase detector for a PLD independent of timing requirements|
|Abstract:||An apparatus and method of compensating for differences in circuit routing path lengths is described. In one embodiment, a latch is inserted between reset signal generating logic and a pair of flip-flops. When a reset signal is generated, the reset signal is held inside the latch until both flip-flops are reset. A latch reset signal may be generated by the flip-flops to clear the latch. The circuit may be configured to ensure that both flip-flops are reset before the reset signal is disabled.|
|Inventor(s):||Lai; David (Mountain View, CA), Wang; Eugene (Fremont, CA)|
|Assignee:||Cisco Technology, Inc. (San Jose, CA)|
Patent Claim Types:|
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