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Claims for Patent: 6,552,616

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Claims for Patent: 6,552,616

Title: Asynchronous phase detector for a PLD independent of timing requirements
Abstract:An apparatus and method of compensating for differences in circuit routing path lengths is described. In one embodiment, a latch is inserted between reset signal generating logic and a pair of flip-flops. When a reset signal is generated, the reset signal is held inside the latch until both flip-flops are reset. A latch reset signal may be generated by the flip-flops to clear the latch. The circuit may be configured to ensure that both flip-flops are reset before the reset signal is disabled.
Inventor(s): Lai; David (Mountain View, CA), Wang; Eugene (Fremont, CA)
Assignee: Cisco Technology, Inc. (San Jose, CA)
Application Number:09/816,948
Patent Claims: 1. An apparatus, comprising: a first flip-flop having an output and a control input; a second flip-flop having an output and a control input; a first logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the first logic gate having an output, wherein the first logic gate is a NOR gate; and a latch having a control input coupled to the output of the logic gate, the latch having an output coupled to the control inputs of the first and second flip-flops, wherein the latch holds a first value until both the outputs of the first and second flip-flops have the same value.

2. The apparatus of claim 1, wherein the latch holds a first value until both the outputs of the first and second flip-flops have the same value.

3. The apparatus of claim 1, wherein the second flip-flop has a clock input coupled to receive an oscillator clock signal.

4. The apparatus of claim 1, wherein the first flip flop has a clock input coupled to receive a reference clock signal.

5. The apparatus of claim 1, wherein the first value is a logical 1 and the same value of the first and second flip-flop outputs is a logical 1.

6. The apparatus of claim 1, further comprising: a second logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the second logic gate having an output coupled to the latch.

7. The apparatus of claim 6, wherein the second logic gate is an AND gate and wherein the AND gate operates to clear the latch.

8. A method, comprising: receiving a first output from a first flip-flop by a NOR gate; receiving a second output from a second flip-flop by the NOR gate; generating a first value for a reset signal by the NOR gate based on the first and second outputs; detecting a state change on the first and second outputs; and holding the first value of the reset signal until the state change is detected on both the first and second outputs.

9. The method of claim 8, wherein the state change indicates that the first and second flip-flops are reset.

10. The method of claim 8, wherein detecting a state change comprises: receiving a third output from the first flip-flop; receiving a fourth output from the second flip-flop; and generating a second value for the reset signal by performing logical operations on the third and fourth outputs.

11. The method of claim 10, wherein the first and second outputs have a bit value of 0.

12. The method of claim 10, wherein the third and fourth outputs have a bit value of 1.

13. The method of claim 10, further comprising changing the reset signal to have the first value.

14. An apparatus, comprising: a phase detector; and means for resetting an output of said phase detector independent of routing path lengths between components internal to said phase detector, wherein the means for resetting comprises a latch disposed between a NOR gate and first and second flip-flops to receive a reset signal and hold the reset signal until both the first and second flip-flops are reset.

15. The apparatus of claim 14, further comprising means for clearing the latch.

16. A phase locked loop, comprising: a voltage controlled oscillator; and a phase detector coupled to the voltage controlled oscillator, the phase detector comprising: a first flip-flop having an output and a control input; a second flip-flop having an output and a control input; a first logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the first logic gate having an output, wherein the first logic gate is a NOR gate; and a latch having a control input coupled to the output of the logic gate, the latch having an output coupled to the control inputs of the first and second flip-flops, wherein the latch holds a first value until both the outputs of the first and second flip-flops have the same value.

17. The phase locked loop of claim 16, wherein the phase detector further comprises a second logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the second logic gate having an output coupled to the latch.

18. The phase locked loop of claim 17, wherein the second logic gate is an AND gate and wherein the AND gate operates to clear the latch.

19. A switch, comprising: a framer; and a phase locked loop coupled to the framer, the phase locked loop comprising: a voltage controlled oscillator; and a phase detector coupled to the voltage controlled oscillator, the phase detector comprising: a first flip-flop having an output and a control input; a second flip-flop having an output and a control input; a first logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the first logic gate having an output, wherein the first logic gate is a NOR gate; and a latch having a control input coupled to the output of the logic gate, the latch having an output coupled to the control inputs of the first and second flip-flops, wherein the latch holds a first value until both the outputs of the first and second flip-flops have the same value.

20. The switch of claim 19, wherein the phase detector further comprises a second logic gate having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop, the second logic gate having an output coupled to the latch.

21. The switch of claim 19, wherein the second logic gate is an AND gate and wherein the AND gate operates to clear the latch.
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