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Claims for Patent: 7,049,230

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Claims for Patent: 7,049,230

Title:Method of forming a contact plug in a semiconductor device
Abstract: A contact plug is formed in a semiconductor device having a silicon substrate having a gate electrode, a junction area and an insulating interlayer. A contact hole is formed to expose the junction area. A plasma process is carried out with respect to a resultant substrate, thereby removing natural oxides created on an exposed surface of the junction area. A first silicon layer is deposited on the contact hole and on the insulating interlayer. A heat-treatment process is carried out with respect to the first silicon layer so as to grow the amorphous silicon into the epitaxial silicon. A second silicon layer is deposited on the first silicon layer.
Inventor(s): Park; Sung Eon (Seoul, KR)
Assignee: Hynix Semiconductor Inc. (Kyoungki-do, KR)
Application Number:10/984,494
Patent Claims: 1. In a semiconductor device having a silicon substrate having a gate electrode, a junction area, and an insulating interlayer, wherein a contact hole exposing the junction area is formed in a portion of the insulating interlayer, a method of forming a contact plug in the contact hole comprising the steps of: i) performing a plasma process removing natural oxides on the exposed surface of the junction area; ii) depositing a first silicon layer in the contact hole without completely filling the contact hole and on the insulating interlayer, wherein the first silicon layer includes epitaxial silicon in the lower portion of the contact hole, amorphous silicon in the portion above the lower portion of the contact hole, and polycrystalline silicon on the insulating interlayer; iii) applying heat to the first silicon layer transforming the amorphous silicon into epitaxial silicon in the portion above the lower portion of the contact hole; iv) depositing a second silicon layer on the first silicon layer; and v) performing a CMP process with respect to the first and second silicon layers so as to expose the insulating interlayer.

2. The method of claim 1, wherein the plasma process is performed under a temperature condition of 200 to 600.degree. C. and a pressure condition of 1 mTorr to 9 Torr while supplying hydrogen and nitrogen gases.

3. The method of claim 2, wherein the flow rate of hydrogen gas is in the range of 20 and 500 sccm, and the flow rate of nitrogen gas is in the range of 0 and 2000 sccm.

4. The method of claim 1, wherein the plasma process is performed in presence of 500 to 2000 W of microwave and a substrate bias voltage of lower than 20 V.

5. The method of claim 1, wherein the first and second silicon layers are deposited by using a dichlorosilane (DCS) gas, a H.sub.2 gas, and a PH.sub.3 gas under a temperature condition of 530 to 650.degree. C.

6. The method of claim 5, wherein the flow rate of the PH.sub.3 gas is in a range of about 0 to 500 sccm.

7. The method of claim 1, wherein the first silicon layer is deposited to a thickness of about 200 to 1500 .ANG..

8. The method of claim 1, wherein the epitaxial silicon of the first silicon layer is grown to a thickness of about 100 to 1000 .ANG..

9. The method of claim 1 further comprising performing a heat-treatment process carried out for the first silicon layer under a hydrogen atmosphere for 2 to 30 minutes at a temperature condition of 550 to 650.degree. C.

10. The method of claim 1 further comprising performing a heat-treatment process carried out for the first silicon layer in-situ during the deposition of the first silicon layer.

11. The method of claim 1, further comprising performing dry and wet cleaning processes on the exposed junction area in the contact hole before performing the plasma process.

12. The method of claim 1, wherein the structures of the first and second silicon layers are substantially identical.
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