Claims for Patent: RE42864

Summary for Patent: RE42864

Title:	Rugged and fast power MOSFET and IGBT
Abstract:	A power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of first conductivity is formed within a well region of second conductivity. The source region is provided proximate to the upper surface of the substrate. The well region has a non-polygon design. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate.
Inventor(s):	Tsukanov; Vladimir (Mountain View, CA), Zommer; Nathan (Fort Lauderdale, FL)
Assignee:	IXYS Corporation (Santa Clara, CA)
Application Number:	11/334,817
Patent Claims:	1. A power semiconductor device, comprising: a substrate having an upper surface and a lower surface; a source region of first conductivity formed within a continuous well region of second conductivity, the source region provided proximate to the upper surface of the substrate, the source region having a first region, a second region, and a third region, the well region having a non-polygon design .Iadd.in a shape of one of a peanut or two overlapping circles.Iaddend.; first and second gate electrodes overlying the upper surface of the substrate; and a drain electrode provided proximate to the lower surface of the substrate, wherein the first region of the source region and the first gate electrode define a first channel, and the second region of the source region and the second gate electrode define a second channel.[...]..Iadd.,.Iaddend. wherein the first and second channels are defined within the well region. 2. The device of claim 1, wherein the well region is a P well region and the source region is an N well region. .[.3. The device of claim 1, wherein the well region has a shape of peanut or two overlapping circles..]. 4. The device of claim 1, wherein a plurality of the well regions are provided proximate to the upper surface wherein a plurality of the source regions are provided. 5. The device of claim 4, wherein the plurality of the well regions define cells of the power device, the cells being coupled to the drain electrode. 6. The device of claim 1, wherein the .[.gate electrode is.]. .Iadd.first and second gate electrodes are formed by .Iaddend.a patterned polysilicon layer, the .[.gate electrode having an opening that is substantially non-polygon.]. .Iadd.first and second gate electrodes defining an opening that is substantially non-polygonal.Iaddend.. 7. The device of claim 1, wherein the source region is an N+ region having a shape of figure 8. 8. The device of claim .[.7.]. .Iadd.1.Iaddend., wherein the .Iadd.source region is an .Iaddend.N+ region .Iadd.and .Iaddend.includes two circular lobes, each lobe having an outer perimeter and an inner perimeter that are both bounded by the well region to define a circular electron current path. 9. The device of claim 8, wherein the well region includes a P+ region and a P region, wherein the P+ region is provided deeper into the substrate than the P region. 10. The device of claim 9, wherein the source region is provided overlying the P+ region. 11. The device of claim 1, wherein the well region includes a first circular lobe, a second circular lobe, and a connecting region joining the first and second lobes, wherein the connecting region is substantially narrower than a diameter of the first or second lobe to provide an electrical crowding effect at the connecting region. 12. A power device, comprising: a substrate having an upper surface and a lower surface; a plurality of cells provided proximate to the upper surface of the substrate, the cells having non-polygon shapes and including source regions defining narrow electrical path within the cells; and a drain electrode provided proximate to the lower surface of the .[.surface.]. .Iadd.substrate.Iaddend., wherein the source region is formed within a continuous well region .Iadd.having a shape of one of a peanut or two overlapping circles.Iaddend., the source region including a .Iadd.first .Iaddend.portion, a second portion, and a third portion, the first portion defining a first circular path, the second portion defining a second circular path, the third portion connecting the first and second circular paths to define a continuous current path. 13. A power semiconductor device, comprising: a substrate having an upper surface and a lower surface; a source region of N conductivity formed within a well region of P conductivity, the source region provided proximate to the upper surface of the substrate and having a first circular path, a second circular path, and a connecting portion connecting the first and second circular paths; a gate electrode overlying the upper surface of the substrate; and a drain electrode provided proximate to the lower surface of the substrate, wherein the connecting portion is configured to provided an increase resistance in the source region, wherein the well region has smooth profiles without angular edges .Iadd.and is formed in a shape of one of a peanut or two overlapping circles.Iaddend.. .[.14. The device of claim 13, wherein the well region has a shape of peanut or two overlapping circles..]. 15. The device of claim 13, wherein the well region includes a first circular section, a second circular section, and a connecting section connecting the first and second circular sections, wherein the connecting section has a width that is substantially less than the a diameter of the first or second circular section. 16. The device of claim 15, wherein the well region defines a cell of the power device, where the power device has a plurality of cells. 17. The device of claim 13, wherein the gate electrode is polysilicon and is patterned to define the well region. 18. The device of claim 17, wherein the gate electrode includes an opening having a first circular opening, a second circular opening, and a connecting portion opening, wherein the connecting portion opening has a linear dimension. 19. The device of claim 13, wherein at least one path of the source region has a varying depth. 20. The device of claim 19, wherein the at least one path includes an inner side having a first depth and an outer side having a second depth, the outer side being proximate to a channel region of the device, the first depth being less than second depth. .[.21. A power semiconductor device, comprising: a substrate having an upper surface and a lower surface; a source region of first conductivity formed within a continuous well region of second conductivity, the source region provided proximate to the upper surface of the substrate, the source region having a first region, a second region, and a third region; first and second gate electrodes overlying the upper surface of the substrate; and a drain electrode provided proximate to the lower surface of the substrate, wherein the first region of the source region and the first gate electrode define a first channel, and the second region of the source region and the second gate electrode define a second channel..]. .[.22. The power device of claim 21, wherein the first, second, and third regions are a continuous region formed with the region and define a continuous path..]. .[.23. The power device of claim 21, wherein the well region includes a P+ region and a P region, wherein the P+ region is provided deeper into the substrate than the P region..]. 24. A power semiconductor device, comprising: a substrate having an upper surface and a lower surface; a source region of N conductivity formed within a well region of P conductivity .Iadd.having one of a peanut shape or two overlapping circles, and the source region includes two circular regions.Iaddend., the source region provided proximate to the upper surface of the substrate and having a first circular path, a second circular path, and a connecting portion connecting the first and second circular paths; a gate electrode overlying the upper surface of the substrate, the gate electrode including an opening having a first circular opening, a second circular opening, and a connecting portion opening, wherein the connecting portion opening has a linear dimension and is configured to provided an increase resistance in the source region; and a drain electrode provided proximate to the lower surface of the substrate. .Iadd.25. A power semiconductor device, comprising: a substrate having an upper surface and a lower surface; a P-well region formed by using a mask having a non-polygon-shaped opening, the P-well being provided proximate the upper surface of the substrate, wherein the P-well region has a shape of a peanut or two overlapping circles; an N-type source region formed within P-well and having a first region, a second region, and a third region; at least one gate electrode overlying the upper surface of the substrate; and a drain electrode provided proximate to the lower surface of the substrate..Iaddend. .Iadd.26. The device of claim 25, wherein the first region of the source region is associated with a first channel, and the second region of the source region is associated with a second channel, and wherein the first and second channels are defined within the P-well region..Iaddend. .Iadd.27. The device of claim 25, wherein the mask used to form the P-well region comprises a patterned polysilicon layer..Iaddend. .Iadd.28. The device of claim 27, wherein the patterned polysilicon layer defines the gate electrode, and wherein the P-well is formed by implanting P-type dopant through the opening of the mask..Iaddend. .Iadd.29. The device of claim 28, wherein the source region has a non-polygon shape, and the opening in the patterned polysilicon includes a first circular region and a second circular region..Iaddend. .Iadd.30. The device of claim 29, wherein the well-region has a peanut shape and the source region includes two circular regions..Iaddend. .Iadd.31. The device of claim 25, wherein the opening in the mask defines the opening of a first circular section and a second circular section, and wherein the P-well is formed by implanting P-type dopants through the opening of the mask..Iaddend. .Iadd.32. The device of claim 31, wherein the opening in the mask has a peanut shape..Iaddend. .Iadd.33. The device of claim 31, wherein the source region has a non-polygon shape..Iaddend. .Iadd.34. The device of claim 33, wherein the source region has a shape of a figure 8..Iaddend.

Details for Patent RE42864

Applicant	Tradename	Biologic Ingredient	Dosage Form	BLA	Approval Date	Patent No.	Expiredate
Aimmune Therapeutics, Inc.	PALFORZIA	peanut (arachis hypogaea) allergen powder	Powder	125696	01/31/2020		2040-02-22