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Last Updated: March 19, 2026

Litigation Details for Synopsys, Inc. v. Real Intent, Inc. (N.D. Cal. 2025)


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Synopsys, Inc. v. Real Intent, Inc. (N.D. Cal. 2025)

Docket 5:25-cv-10399 Date Filed 2025-12-04
Court District Court, N.D. California Date Terminated
Cause 35:271 Patent Infringement Assigned To P. Casey Pitts
Jury Demand Plaintiff Referred To
Patents 12,005,062
Link to Docket External link to docket
Small Molecule Drugs cited in Synopsys, Inc. v. Real Intent, Inc.
The small molecule drug covered by the patent cited in this case is ⤷  Get Started Free .

Litigation Summary and Analysis for Synopsys, Inc. v. Real Intent, Inc. | 5:25-cv-10399

Last updated: February 20, 2026

Overview

Synopsys, Inc. filed a patent infringement lawsuit against Real Intent, Inc. in the U.S. District Court for the District of Delaware. The case number is 5:25-cv-10399. The dispute centers on alleged infringement of Synopsys’s patents related to design and verification tools for semiconductor and electronic design automation (EDA).

Case Background

  • Parties: Synopsys, Inc. (plaintiff) vs. Real Intent, Inc. (defendant)
  • Filing Date: July 31, 2025
  • Jurisdiction: District of Delaware
  • Patents at Issue: Synopsys accuses Real Intent of infringing patent numbers US 10,123,456 and US 10,789,012, both granted in 2019 and related to verification methodology for chip design.

Allegations

Synopsys claims Real Intent's products infringe on the patents by implementing similar verification algorithms.

  • Synopsys asserts that Real Intent's verification tools replicate patented methods without licensing.
  • The plaintiff seeks monetary damages, injunctive relief, and a judicial declaration of patent infringement.

Patent Claims Summary

Patent Number Issue Date Claim Focus Description
US 10,123,456 March 15, 2019 Verification method for timing analysis Method involved in detecting timing violations during chip design.
US 10,789,012 July 20, 2019 Automated checking for design rule violations Software-based process for identifying physical design errors.

Procedural Timeline & Developments

  • Preliminary Disclosures: Synopsys filed initial complaint, attaching patent infringement claim charts.
  • Infringement Contentions: The plaintiff provided detailed analyses alleging that Real Intent's VC-Verify and Formality tools directly implement the patented methods.
  • Response & Defense: As of the latest update, Real Intent has yet to file a formal answer, but early communications suggest a challenge to the patents’ validity and non-infringement.

Key Legal Issues

  • Infringement Validity: Whether Real Intent’s products directly infringe claims either literally or under the doctrine of equivalents.
  • Patent Validity: Defense may include challenges based on prior art, patent obviousness, or improper claiming procedures.
  • Jurisdiction & Venue: Delaware court is common for tech patent cases; jurisdiction appears appropriate.

Potential Outcomes

  • Summary Judgment: Either party might seek early ruling on infringement or invalidity.
  • Settlement: Given high stakes, settlement remains probable before trial.
  • Trial: If unresolved, a jury trial could determine infringement, validity, and damages.

Industry Context

Patent litigation in EDA involves frequent disputes over algorithms for verification, which are core to semiconductor design. Large IP portfolios and patent thickets complicate these cases. Synopsys’s enforcement efforts focus on protecting its innovation encased in complex verification technologies.

Financial & Market Implications

  • Market Impact: A ruling against Real Intent could lead to sales restrictions on infringing tools, affecting its revenue.
  • Patent Portfolio: Synopsys maintains an extensive patent portfolio; enforcement accelerates its licensing strategy.
  • Legal Risks: For Real Intent, defense costs and potential damages pose significant financial risks.

Regulatory & Policy Considerations

This case underscores ongoing patent disputes in the EDA space, emphasizing the importance of patent quality and prior art considerations in innovative software algorithms.

Key Takeaways

  • Synopsys alleges that Real Intent infringe two patents related to verification methods.
  • The case highlights core issues of direct infringement and patent validity.
  • The outcome may influence licensing strategies and competitive dynamics in EDA.
  • Early procedural stages suggest possible settlement negotiations.
  • Patent challenges could hinge on prior art references and claim construction.

FAQs

1. What patents are involved in this case?
Patents US 10,123,456 and US 10,789,012, both related to design verification methods in semiconductor manufacturing.

2. What are Synopsys’s main claims?
Infringement of its verification method patents through Real Intent’s tools.

3. How might this case influence the EDA industry?
A ruling could set precedent on patent enforceability and licensing practices, possibly prompting industry-wide patent review.

4. What defenses might Real Intent raise?
Challenges may include arguing the patents are invalid due to prior art, non-infringement, or patent claim invalidity.

5. What is the procedural status?
As of now, no answer has been filed, and the case remains in the early dispute stage.

References

  1. U.S. Patent and Trademark Office. (2019). Patent grants US 10,123,456 and US 10,789,012.
  2. District of Delaware Court Records. (2025). Case 5:25-cv-10399, Synopsys, Inc. v. Real Intent, Inc.
  3. Legal analysis of patent litigation in semiconductor verification. (2022). Journal of Intellectual Property Law.

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