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Details for Patent: 7,821,557

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Details for Patent: 7,821,557

Title:High speed sampling of signals in active pixel sensors using buffer circuitry
Abstract: Techniques are disclosed for enhancing the speed at which pixel levels are read out and sampled for processing. A method of processing pixel levels includes clamping a pixel readout line to a voltage level less than a voltage corresponding to a signal sensed by an n-MOS pixel. Subsequently, the pixel readout line is coupled to an output of an n-MOS source-follower and the pixel signal is read out onto the pixel readout line through the n-MOS source-follower. The pixel signal that was read out is passed through a p-MOS source-follower to a processing circuit. Before passing the pixel signal through the p-MOS source-follower to the processing circuit, a capacitive storage node in the processing circuit is clamped to a voltage greater than a signal at an input to the p-MOS source-follower. Subsequently, an output of the p-MOS source-follower is coupled to the processing circuit, and a signal corresponding to the pixel signal is stored by the processing circuit. Similar techniques are provided for reading out and sampling p-MOS pixels.
Inventor(s): Bock; Nikolai E. (Pasadena, CA), Krymski; Alexander I. (Montrose, CA), Mansoorian; Barmak (San Diego, CA)
Assignee: Aptina Imaging Corp. (Grand Cayman, KY)
Filing Date:Jun 23, 2006
Application Number:11/473,130
Claims:1. An imager comprising: a pixel readout line; an active pixel sensor including an n-MOS source-follower through which signals sensed by the sensor can be read out to the pixel readout line, a first switch that can be enabled to read out signals from the sensor, and a reset switch; a buffer circuit coupled to the pixel readout line including a p-MOS source-follower and a second p-MOS transistor configured as a current sink connected to a source of the p-MOS source-follower; a processing circuit including sample and hold circuitry having an input coupled to an output of the buffer circuit such that signals being sampled and held by the processing circuit are first buffered by the buffer circuit; and a controller configured to provide control signals to cause the pixel readout line to be clamped to a voltage level less than a voltage corresponding to a signal sensed by the sensor, and subsequently to cause the sensor signal to be read out through the n-MOS source-follower to the pixel readout line and to be passed to the processing circuit through the p-MOS source-follower.

2. The imager of claim 1 wherein the controller is configured to provide a control signal to cause a capacitive storage node in the processing circuit to be clamped to a voltage greater than the sensor signal at an input to the p-MOS source-follower, wherein the storage node is clamped before passing the sensor signal through the p-MOS source-follower to the processing circuit, and wherein the controller is configured to provide a control signal to cause an output of the p-MOS source-follower subsequently to be coupled to the storage node in the processing circuit.

3. The imager of claim 2 wherein the processing circuit includes a clamping switch that is coupled to the storage node and that selectively can be closed to clamp the storage node to the voltage greater than the sensor signal, and wherein the controller is configured to provide a control signal to cause the clamping switch in the processing circuit to be temporarily closed before causing the output of the p-MOS source-follower to be coupled to the storage node.

4. The imager of claim 2 wherein, when the output of the p-MOS source-follower is coupled to the storage node, the processing circuit stores a signal corresponding to the sensor signal, and wherein the controller is configured to provide control signals to cause the reset switch subsequently to be enabled, and to cause a reset signal to be read out from the sensor through the n-MOS source-follower and passed through the p-MOS source-follower to the processing circuit such that the processing circuit stores a signal corresponding to the reset signal on a second capacitive storage node.

5. The imager of claim 1, wherein the buffer circuit further comprises an n-MOS transistor configured as a power enable switch and connected in series with the first p-MOS transistor.

6. The imager of claim 1, wherein the processing circuit further comprises a binary scaled capacitor network adapted to convert a sampled signal to a digital value.

7. An imager comprising: a pixel readout line; an active pixel sensor including a p-MOS source-follower through which signals sensed by the sensor can be read out to the pixel readout line, a first switch that can be enabled to read out signals from the sensor, and a reset switch; a buffer circuit coupled to the pixel readout line including an n-MOS source-follower and a second n-MOS transistor connected to a source of the n-MOS source-follower; a processing circuit including sample and hold circuitry having an input coupled to an output of the buffer circuit such that signals being sampled and held by the processing circuit are first buffered by the buffer circuit; and a controller configured to provide control signals to cause the pixel readout line to be clamped to a voltage level greater than a voltage corresponding to a signal sensed by the sensor, and subsequently to cause the sensor signal to be read out through the p-MOS source-follower to the pixel readout line and to be passed to the processing circuit through the n-MOS source-follower.

8. The imager of claim 7 wherein the controller is configured to provide a control signal to cause a capacitive storage node in the processing circuit to be clamped to a voltage less than the sensor signal at an input to the n-MOS source-follower, wherein the storage node is clamped before passing the sensor signal through the n-MOS source-follower to the processing circuit, and wherein the controller is configured to provide a control signal to cause an output of the n-MOS source-follower subsequently to be coupled to the storage node in the processing circuit.

9. The imager of claim 7 wherein the processing circuit includes a clamping switch that is coupled to the storage node and that selectively can be closed to clamp the node to the voltage less than the sensor signal, and wherein the controller is configured to provide a control signal to cause the clamping switch in the processing circuit to be temporarily closed before causing the output of the n-MOS source-follower to be coupled to the storage node.

10. The imager of claim 7 wherein, when the output of the n-MOS source-follower is coupled to the storage node, the processing circuit stores a signal corresponding to the sensor signal, and wherein the controller is configured to provide control signals to cause the reset switch subsequently to be enabled, and to cause a reset signal to be read out from the sensor through the p-MOS source-follower and passed through the n-MOS source-follower to the processing circuit such that the processing circuit stores a signal corresponding to the reset signal.

11. The imager of claim 7, wherein the buffer circuit further comprises a p-MOS transistor configured as a power enable switch and connected in series with the first n-MOS transistor.

12. The imager of claim 7, wherein the processing circuit further comprises a binary scaled capacitor network adapted to convert a sampled signal to a digital value.
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