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Details for Patent: 7,630,011

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Details for Patent: 7,630,011

Title:High-speed sampling of signals in active pixel sensors
Abstract: Techniques are disclosed for enhancing the speed at which pixel levels are read out and sampled for processing. A method of processing pixel levels includes clamping a pixel readout line to a voltage level less than a voltage corresponding to a signal sensed by an n-MOS pixel. Subsequently, the pixel readout line is coupled to an output of an n-MOS source-follower and the pixel signal is read out onto the pixel readout line through the n-MOS source-follower. The pixel signal that was read out is passed through a p-MOS source-follower to a processing circuit. Before passing the pixel signal through the p-MOS source-follower to the processing circuit, a capacitive storage node in the processing circuit is clamped to a voltage greater than a signal at an input to the p-MOS source-follower. Subsequently, an output of the p-MOS source-follower is coupled to the processing circuit, and a signal corresponding to the pixel signal is stored by the processing circuit. Similar techniques are provided for reading out and sampling p-MOS pixels.
Inventor(s): Bock; Nikolai E. (Pasadena, CA), Krymski; Alexander I. (Montrose, CA), Mansoorian; Barmak (San Diego, CA)
Assignee: Aptina Imaging Corporation (KY)
Filing Date:Mar 17, 2000
Application Number:09/527,422
Claims:1. A method of processing pixel signals, the method comprising: clamping a pixel readout line to a voltage level less than a voltage corresponding to a pixel signal; subsequently coupling the pixel readout line to an output of a source-follower transistor and reading out the pixel signal onto the pixel readout line; subsequently clamping a capacitive storage node in a pixel signal processing circuit to a voltage less than a voltage corresponding to the pixel signal appearing on the pixel readout line; subsequently coupling the pixel readout line to the storage node in the processing circuit; and storing a signal corresponding to the pixel signal that was read out on the capacitive storage node.

2. The method of claim 1, wherein clamping the pixel readout line comprises discharging a capacitance on the pixel readout line.

3. The method of claim 2, wherein discharging the pixel readout line is performed while processing a previously-stored pixel signal.

4. The method of claim 2, wherein the discharging the capacitance on the pixel readout line comprises disabling a pixel selection switch.

5. The method of claim 2, wherein the discharging the capacitance on the pixel readout line comprises enabling a switch to couple the pixel readout line to ground.

6. The method of claim 1 wherein the storage node is clamped to substantially the same voltage and at about the same time as the pixel readout line.

7. The method of claim 1, further comprising: resetting the pixel; subsequently reading out a reset signal through an n-MOS source-follower; and storing on a second capacitive storage node in the processing circuit a signal that corresponds to the reset signal.

8. The method of claim 7, further comprising: prior to storing the signal corresponding to the reset signal, clamping the second capacitive storage node to a voltage less than the voltage corresponding to the reset signal; and subsequently coupling the pixel readout line to the second storage node to store the signal corresponding to the reset signal on the second storage node.

9. The method of claim 1, further comprising passing the pixel signal that was read out through a p-MOS source-follower.

10. The method of claim 9, further comprising: clamping a capacitive storage node in a pixel signal processing circuit to a voltage greater than the pixel signal appearing at an input to the p-MOS source-follower, wherein the storage node is clamped before passing the pixel signal through the p-MOS source-follower to the processing circuit; and subsequently coupling an output of the p-MOS source-follower to the storage node in the processing circuit.

11. The method of claim 10, further comprising: resetting the pixel after storing the signal corresponding to the pixel signal in the processing circuit; subsequently reading out a reset signal through an n-MOS source-follower; passing the reset signal through the p-MOS source-follower to the processing circuit; and storing a signal corresponding to the reset signal in the processing circuit.

12. The method of claim 11, wherein, prior to passing the reset signal through the p-MOS source-follower, a second capacitive storage node in the processing circuit is clamped to a voltage level higher than the reset signal appearing at the input to the p-MOS source-follower.

13. The method of claim 11, further comprising converting a difference between the pixel and reset signals stored by the processing circuit to a corresponding set of digital signals.

14. The method of claim 1, wherein the reading out the pixel signal onto the pixel readout line comprises reading out the pixel signal through the source-follower transistor.

15. The method of claim 14, wherein the source-follower transistor comprises an n-MOS transistor.

16. The method of claim 1, wherein the capacitive storage node comprises a binary scaled capacitor network.

17. An imager comprising: a pixel readout line; an active pixel sensor comprising a source-follower transistor through which signals sensed by the sensor can be read out to the pixel readout line, a first switch that can be enabled to read out signals from the sensor, and a reset switch; a signal processing circuit that can be coupled to the pixel readout line; and a controller configured to provide control signals to cause the pixel readout line to be clamped to a voltage level less than a voltage corresponding to a signal sensed by the sensor, and subsequently to cause the sensor signal to be read out through the source-follower transistor to the pixel readout line and to be stored by the processing circuit, wherein the processing circuit comprises a capacitive storage node, and wherein the controller is further configured to provide control signals to subsequently cause the capacitive storage node to be clamped to a voltage less than a voltage corresponding to the sensor signal appearing on the pixel readout line, and subsequently to cause the pixel readout line to be coupled to the storage node.

18. The imager of claim 17, wherein the controller is configured to provide a control signal to cause the first switch to be disabled while a previously-stored sensor signal is being processed by the processing circuit.

19. The imager of claim 17, further comprising: a third switch coupled between the pixel readout line and ground, wherein the controller is configured provide a control signal to cause the pixel readout line to be clamped by enabling the third switch.

20. The imager of claim 17, wherein the storage node is clamped to substantially the same voltage and at about the same time as the pixel readout line.

21. The imager of claim 17, wherein: the processing circuit further comprises a second capacitive storage node, and the controller is configured to provide control signals to cause the reset switch in the pixel to be enabled, and subsequently to cause a reset signal to be read out onto the pixel readout line through the source-follower transistor, and to cause a signal that corresponds to the reset signal to be stored on the second capacitive storage node.

22. The imager of claim 17, wherein the capacitive storage node comprises a binary scaled capacitor network.
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