.

Pharmaceutical Business Intelligence

  • Anticipate P&T budget requirements
  • Evaluate market entry opportunities
  • Find generic sources and suppliers
  • Predict branded drug patent expiration

► Plans and Pricing

Upgrade to enjoy subscriber-only features like email alerts and data export. See the Plans and Pricing

DrugPatentWatch Database Preview

Details for Patent: 6,399,982

« Back to Dashboard

Details for Patent: 6,399,982

Title: Rough (high surface area) electrode from Ti and TiN capacitors and semiconductor devices including same
Abstract:A technique for forming a high surface area electrode or storage node for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.
Inventor(s): Derderian; Garo J. (Boise, ID), Sandhu; Gurtej S. (Boise, ID)
Assignee: Micron Technology, Inc. (Boise, ID)
Filing Date:Jul 15, 1999
Application Number:09/353,426
Claims:1. A storage node structure for a semiconductor capacitor including a discontinuous layer of a first conductive material defining a plurality of exposed areas on a substrate surface and a second conductive material layer exteding over said first conductive material of said discontinuous layer and said plurality of exposed areas of said substrate surface such that said second conductive material layer exhibits a thickness over said first conductive material of said discontinuous layer greater than a thickness over said plurality of exposed areas of said substrate, said storage node structure formed by a method comprising:

providing a substrate;

depositing said discontinuous layer of said first conductive material on said substrate, wherein said discontinuous layer of said first conductive material defines said plurality of exposed areas on said substrate surface; and

depositing said layer of said second conductive material over said first conductive material of said discontinuous layer and said plurality of exposed areas of said substrate surface, wherein said layer of said second conductive material forms on said first conductive material of said discontinuous layer at a faster rate than on said plurality of exposed areas defined by said discontinuous layer of said first conductive material.

2. The storage node structure of claim 1, wherein said substrate includes a via and wherein said discontinuous layer of said first conductive material forms on walls of said via.

3. The storage node structure of claim 1, wherein said capacitor includes a capacitor structure formed in said substrate and wherein said discontinuous layer of said first conductive material forms on walls of said capacitor structure.

4. The storage node structure of claim 1, wherein said substrate includes borophosphosilicate glass.

5. The storage node structure of claim 1, wherein depositing said discontinuous layer of said first conductive material includes a deposition technique selected from the group comprising sputter deposition.

6. The storage node structure of claim 1, wherein depositing said layer of said second conductive material includes a deposition technique selected from the group comprising sputter deposition and chemical vapor deposition.

7. The storage node structure of claim 1, wherein said discontinuous layer of said first conductive material comprises titanium and said layer of said second conductive material comprises titanium nitride.

8. The storage node structure of claim 7, wherein said titanium layer is deposited by a collimated sputtering technique.

9. The storage node structure of claim 8, wherein said titanium layer deposition includes a temperature of between about 20 and 600.degree. C.

10. The storage node structure of claim 8, wherein said titanium layer deposition includes a temperature of between about 300 and 400.degree. C.

11. The storage node structure of claim 8, wherein said titanium layer deposition includes a pressure of between about 0.4 mTorr and 1.0 Torr.

12. The storage node structure of claim 8, wherein said titanium layer deposition includes a pressure of about 0.6 mTorr.

13. The storage node structure of claim 7, wherein said titanium nitride layer is deposited by a chemical vapor deposition technique.

14. The storage node structure of claim 13, wherein said titanium nitride layer deposition includes a temperature of between about 300 and 500.degree. C.

15. The storage node structure of claim 13, wherein said titanium nitride layer deposition includes a temperature of about 420.degree. C.

16. The storage node structure of claim 13, wherein said titanium nitride layer deposition includes a pressure of between about 40 mTorr and 10 Torr.

17. The storage node structure of claim 13, wherein said titanium nitride layer deposition includes a pressure of about 600 mTorr.

18. The storage node structure of claim 1, wherein depositing said layer of said second conductive material over said first conductive material of said discontinuous layer forms nodules of titanium nitride over segments of said first conductive material.

19. The storage node structure of claim 18, wherein said titanium nitride nodules include diameters of about 500 angstroms.

20. A semiconductor device comprising a capacitor including a storage node structure having a discontinuous layer of a first conductive material, a plurality of exposed areas on a substrate surface and a layer of a second conductive material over said first conductive material of said discontinuous layer and said plurality of exposed areas of said substrate surface such that said layer of second conductive material exhibits a thickness over said first conductive material of said discontinuous layer greater than a thickness over said plurality of exposed areas of said substrate, said storage node structure formed by a method comprising:

providing a substrate;

depositing said discontinuous layer of said first conductive material on a surface of said substrate, wherein said discontinuous layer of said first conductive material defines said plurality of exposed areas on said substrate surface; and

depositing said layer of said second conductive material over said first conductive material of said discontinuous layer and said plurality of exposed areas on said substrate surface, wherein said layer of said second conductive material grows or accumulates on said first conductive material of said discontinuous layer at a faster rate than on said plurality of exposed areas defined by said discontinuous layer of said first conductive material.

21. The semiconductor device of claim 20, wherein said substrate includes a via and wherein said discontinuous layer of said first conductive material forms on walls of said via.

22. The semiconductor device of claim 20, wherein said capacitor includes a capacitor structure formed in said substrate and wherein said discontinuous layer of said first conductive material forms on walls of said capacitor structure.

23. The semiconductor device of claim 20, wherein said substrate includes borophosphosilicate glass.

24. The semiconductor device of claim 20, wherein depositing said discontinuous layer of said first conductive material includes a deposition technique selected from the group comprising sputter deposition and chemical vapor deposition.

25. The semiconductor device of claim 20, wherein depositing said layer of said second conductive material includes a deposition technique selected from the group comprising sputter deposition and chemical vapor deposition.

26. The semiconductor device of claim 20, wherein said discontinuous layer of said first conductive material comprises titanium and said layer of said second conductive material comprises titanium nitride.

27. The semiconductor device of claim 26, wherein said titanium layer is deposited by a collimated sputtering technique.

28. The semiconductor device of claim 27, wherein said titanium layer deposition includes a temperature of between about 20 and 600.degree. C.

29. The semiconductor device of claim 27, wherein said titanium layer deposition includes a temperature of between about 300 and 400.degree. C.

30. The semiconductor device of claim 27, wherein said titanium layer deposition includes a pressure of between about 0.4 mTorr and 1.0 Torr.

31. The semiconductor device of claim 27, wherein said titanium layer deposition includes a pressure of about 0.6 mTorr.

32. The semiconductor device of claim 26, wherein said titanium nitride layer is deposited by a chemical vapor deposition technique.

33. The semiconductor device of claim 32, wherein said titanium nitride layer deposition includes a temperature of between about 300 and 500.degree. C.

34. The semiconductor device of claim 32, wherein said titanium nitride layer deposition includes a temperature of about 420.degree. C.

35. The semiconductor device of claim 32, wherein said titanium nitride layer deposition includes a pressure of between about 40 mTorr and 10 Torr.

36. The semiconductor device of claim 32, wherein said titanium nitride layer deposition includes a pressure of about 600 mTorr.

37. The semiconductor device of claim 20, wherein depositing said layer of said second conductive material over said first conductive material of said discontinuous layer forms nodules of titanium nitride over segments of said first conductive material.

38. The semiconductor device of claim 37, wherein said titanium nitride nodules include diameters of about 500 angstroms.

39. A capacitor storage node, comprising:

a discontinuous layer of a first conductive material on a substrate, said discontinuous first conductive material layer defining a plurality of exposed areas on said substrate; and

a layer of a second conductive material over said discontinuous layer of said first conductive material and said plurality of exposed areas on said substrate, wherein said layer of second conductive material exhibits a thickness over said first conductive material of said discontinuous layer greater than a thickness over said plurality of exposed areas of said substrate.

40. The capacitor storage node of claim 39, wherein said first conductive material comprises titanium and said second conductive material comprises titanium nitride.

41. The capacitor storage node of claim 40, wherein said substrate includes borophosphosilicate glass.

42. A memory cell having at least one capacitor storage node, comprising:

a discontinuous layer of a first conductive material on a substrate, said discontinuous first conductive material layer defining a plurality of exposed areas on said substrate; and

a layer of a second conductive material over said discontinuous layer of said first conductive material and said plurality of exposed areas on said substrate, wherein said layer of second conductive material exhibits a thickness over said first conductive material of said discontinuous layer greater than a thickness over said plurality of exposed areas of said substrate.

43. The memory cell of claim 42, wherein said first conductive material comprises titanium and said second conductive material comprises titanium nitride.

44. The memory cell of claim 43, wherein said substrate includes borophosphosilicate glass.

45. A random access memory chip having at least one memory cell having at least one capacitor storage node, comprising:

a discontinuous layer of a first conductive material on a substrate, said discontinuous first conductive material layer defining a plurality of exposed areas on said substrate; and

a layer of a second conductive material over said discontinuous layer of said first conductive material and said plurality of exposed areas on said substrate, wherein said layer of second conductive material exhibits a thickness over said first conductive material of said discontinuous layer greater than a thickness over said plurality of exposed areas of said substrate.

46. The random access memory chip of claim 45, wherein said first conductive material comprises titanium and said second conductive material comprises titanium nitride.

47. The random access memory chip of claim 46, wherein said substrate includes borophosphosilicate glass.
« Back to Dashboard

For more information try a trial or see the database preview and plans and pricing

Drugs may be covered by multiple patents or regulatory protections. All trademarks and applicant names are the property of their respective owners or licensors. Although great care is taken in the proper and correct provision of this service, thinkBiotech LLC does not accept any responsibility for possible consequences of errors or omissions in the provided data. The data presented herein is for information purposes only. There is no warranty that the data contained herein is error free. thinkBiotech performs no independent verifification of facts as provided by public sources nor are attempts made to provide legal or investing advice. Any reliance on data provided herein is done solely at the discretion of the user. Users of this service are advised to seek professional advice and independent confirmation before considering acting on any of the provided information. thinkBiotech LLC reserves the right to amend, extend or withdraw any part or all of the offered service without notice.

`abc